The present invention relates to a solid-state imaging device and a method for manufacturing this device, and more particularly relates to a solid-state imaging device having a charge coupled device, and to a method for manufacturing this solid-state imaging device.
Solid-state imaging devices such as a CCD (Charge Coupled Device) generally include interline types and frame transfer types, among others.
With the above-mentioned frame transfer type, a plurality of light receiving elements called pixels are formed on a p-type silicon substrate surface, for example, dividing [the surface] into a light receiving portion and a transfer (accumulation) portion. With the pixels formed in each portion, a gate electrode is formed via a gate insulating film over a substrate, and a positive potential is applied to this gate electrode, which forms potential wells at the surface portion of the substrate, and when the pixels in the light receiving portion are irradiated with light for a specific length of time, a signal charge is generated in proportion to the amount of light, and is accumulated in the potential wells.
When clock voltage pulses of two different timings, for instance, are applied to the gate electrode of a plurality of pixels in a row, the barriers of the potential wells are successively opened and closed, and the signal charges are successively transferred from the light receiving portion to the transfer portion.
The transferred signal charges are outputted by clock [signals] having a different timing from the above-mentioned clock [signals] in a register portion, and can be outputted as video signals through an output amplifier or the like.
Thus, a CCD allows optical signals to be converted into signal charges, and are currently in use in a wide range of industrial and consumer imaging devices.
The above-mentioned CCD or other solid-state imaging device is usually equipped with an overflow drain that sweeps away excess signal charges in order to prevent overflowing signal charges from being trapped in the potential wells of other pixels when the signal charges exceed the capacity of the potential wells. Overflow drains are broadly classified into two groups: vertical overflow drains (VOD) and lateral overflow drains (LOD).
FIG. 3a is a cross section of a first conventional example of the above-mentioned lateral overflow drain.
A lateral overflow drain (LOD) is formed such that a channel separation layer (not shown) is divided at the boundary between two adjacent pixels (PC1 and PC2) separated by the channel separation layer.
In these pixel regions (PC1 and PC2), an n-type buried channel 11 that serves as a CCD transfer path is formed in a p-type semiconductor substrate 10, and a p+ inversion layer 15 is formed at the surface layer thereof.
The above-mentioned n-type buried channel 11 is formed by communicating with the lateral overflow drain LOD at the boundary of the above-mentioned two pixel regions (PC1 and PC2). An n+ region 18 is formed in the surface layer of the n-type buried channel 11 in the center of the lateral overflow drain LOD so as to connect with the n-type buried channel 11. A p-type region 17 into which p-type impurities have been introduced to the extent that complete inversion does not occur is formed on the surface of the n-type buried channel 11 around the annular outer periphery of the n+ region 18 including the n+ region 18 and the p+ inversion layer 15.
A gate insulating film 20 of silicon oxide is formed over the substrate, an annular gate electrode 33 is formed over the gate insulating film 20, and a wiring layer 34 composed of aluminum, silicon-containing aluminum, or the like is formed so as to fill an opening CH in the gate insulating film 20 in the center of this annular shape, connect to the n+ region 18, and also connect to the gate electrode 33.
In the above structure, the n+ region 18 serves as the drain and the n-type buried channel 11 of the pixel regions (PC1 and PC2) as the source, creating a MOS field effect transistor in which the drain and gate are short-circuited and which has an annular channel formation region around the outer periphery of the n+ region 18 and the gate electrode 33 over the gate insulating film 20.
FIG. 3(b) is a potential diagram in the direction parallel to the surface of the p-type semiconductor substrate 10 of the lateral overflow drain LOD with the above structure.
The p-type region 17 formed at the boundary of the n+ region 18 and the n-type buried channel 11 of the pixel regions (PC1 and PC2) forms a barrier (potential barrier) to signal charges, and a well (potential well) is formed in the outer direction thereof (the direction of the pixel regions (PC1 and PC2)), in which signal charges (electrons) are accumulated.
If the signal charges exceed the capacity of the potential well, the excess signal charges go over the barrier formed by the p-type region 17 and are swept away to the n+ region (drain) 18.
The method for manufacturing the above-mentioned lateral overflow drain LOD will now be described.
First, as shown in FIG. 4(a), a silicon oxide layer is formed by thermal oxidation, CVD, or another such method over the p-type semiconductor substrate 10, forming the gate insulating film 20.
Next, the n-type buried channel 11 is formed by the ion implantation of an n-type conductive impurity D1, such as phosphorus, over the entire surface.
Next, as shown in FIG. 4(b), a resist film R1 is formed by a photolithography process in a pattern that opens up the lateral overflow drain formation region, and a p-type impurity D2 such as boron is introduced by ion implantation to the extent that complete inversion does not occur, thereby forming the p-type region 17 at the surface layer of the n-type buried channel 11.
Next, as shown in FIG. 4(c), the resist film R1 is removed, after which a polysilicon film containing a conductive impurity is formed over the entire surface by CVD, for instance, a resist film (not shown) is formed in the pattern of an annular gate electrode, and etching such as RIE (Reactive Ion Etching) is performed to form the annular gate electrode 33.
Next, as shown in FIG. 5(d), a resist film R2 is formed by a photolithography process in a pattern that opens up the region that becomes the drain, an n-type impurity D3 such as arsenic is introduced by ion implantation, and the n+ region 18 is formed so as to connect to the n-type buried channel 11.
The gate electrode 33 is used as a mask in the ion implantation of the above-mentioned n-type impurity D3 here, so the resist film R2 is formed in a pattern that covers roughly half of the gate electrode 33.
Next, as shown in FIG. 5(e), the resist film R2 is removed, after which a resist film R3 is formed in a pattern covering the region that becomes the drain, and the surface p+ inversion layer 15 is formed by the ion implantation of a p-type impurity D4. Here, the p-type region 17 is formed in a wider pattern than the gate electrode 33, and the p-type region 17 is formed so that it protrudes from under the gate electrode 33, and as a result the p+ inversion layer 15 and the p-type region 17 are connected by a somewhat overlapping portion.
Next, as shown in FIG. 6(f), the resist film R3 is removed and silicon oxide is deposited over the entire surface covering the gate electrode 33 by CVD, for instance, forming an interlayer insulating film 21.
Next, a resist film R4 is formed by a photolithography process in a pattern that opens up the region that becomes the drain, just as with the resist film R2.
Next, as shown in FIG. 6(g), the interlayer insulating film 21 and the gate insulating film 20 are etched by RIE or other etching using the resist film R4 as a mask so as to have a selectivity ratio with respect to the gate electrode 33, forming the opening CH that exposes the n+ region 18. After this the resist film R4 is removed.
Next, [pure] aluminum or aluminum containing about 1% silicon is deposited over the entire surface by sputtering using DC magnetron discharge or another such method so as to connect to the n+ region 18 and the gate electrode 33, which fills in the opening CH. After this, the wiring layer 34 is formed through photolithography and dry etching, for example, which results in the structure shown in FIG. 3(a).
With the above CCD, a reduction in pixel size is accompanied by a reduction in the gate design dimensions (design rule). For example, with state-of-the-art devices, the minimum gate design dimensions are about to go from half-micron to sub-micron, and in wiring such as the wiring layer wiring such as the wiring layer 34 connected to the n+ region 18, the contact diameter or pier hole diameter is being reduced to the half-micron (0.5 xcexcm) level.
However, the above-mentioned pixel size, contact diameter, and so forth continue to be reduced, and when, as shown in FIG. 17, the contact diameter (ØCH) is reduced to 0.8 xcexcm or less and the contact hole aspect ratio (contact hole depth DP: contact diameter ØCH) rises above 1:1, then if, for example, the above-mentioned wiring layer is formed from a conductive material such as [pure] aluminum or aluminum containing about 1% silicon, the film thus formed will have greater overhang and step coverage will not be as good, which tends to lead to contact coverage flaws F where the barrier portion near the contact bottom is not covered by the conductive material.
When the above-mentioned wiring layer is formed from aluminum, the aluminum will be in contact with the silicon substrate, so aluminum alloy spikes S tend to be produced when the aluminum draws up the silicon in the substrate, or when the aluminum diffuses into substrate, for example, during the various treatment steps including sintering (such as 30 minutes at 450xc2x0 C.) carried out for any of a variety of purposes, such as removal at the interfacial level by hydrogen treatment, transistor threshold adjustment, or promotion of aluminum crystallization, and these spikes result in severe leak current at shallow p-n or n-p junctions.
One way to avoid the formation of these alloy spikes is to add about 1% silicon to the aluminum that will become the wiring layer in contact with the substrate, thereby preventing the silicon from being drawn up from the substrate and stopping the formation of the alloy spikes S, but in this case, as shown in FIG. 19, the silicon concentration of the contact bottom portion R rises (the silicon precipitates) in the treatment steps following the formation of the wiring layer, so even when a relatively large contact hole diameter of about 1.4 xcexcm is used, there tends to be a problem in that the contact resistance is too high (about 3000 xcexa9).
One method that is known and widely used with DRAM (Dynamic Random Access Memory), logic devices, and so forth in order to avoid the above problems such as alloy spikes and increased contact resistance involves forming a barrier metal film comprising a titanium (Ti)/titanium nitride (TiN) deposited film by collimation sputtering or other such method, then performing a suitable annealing treatment, and finally forming a tungsten (W) film by CVD.
FIG. 20(a) is a cross section of a lateral overflow drain when the above method is employed for the contact connection of a lateral overflow drain. A barrier metal film 34a comprising a Ti/TiN deposited film is formed, after which a suitable annealing treatment is performed, and a W film 34b is then formed by deposition.
Nevertheless, although the above problems of alloy spike production, increased contact resistance, and so forth can indeed be solved when the above structure in which the barrier metal film 34a (a Ti/TiN deposited film) and the W film 34b are deposited is used in a CCD application, a new problem occurs in that there is a dramatic increase in dark current, which is a critical problem for an imaging device.
FIG. 20(b) is a graph produced by measuring the dark current (relative value) when the wiring for contact connection in a CCD (7.2 xcexcm pixels) with a virtual gate structure having a 1.4 xcexcm contact diameter is formed from (A) aluminum containing about 1% silicon, (B) a Ti (thickness: 50 nm)/TiN/W deposited film, and (C) Ti (thickness: 100 nm)/TiN/W deposited film was used, and then plotting this against cumulative probability.
It was confirmed from FIG. 20(b) that dark current is markedly increased by the use of a Ti/TiN/W deposited film, and is further increased when the Ti film is made thicker.
An aluminum reflow method, a high-pressure aluminum fill method, a CVD aluminum method, and the like have been disclosed in an effort to form the above-mentioned contact wiring for a DRAM, logic device, and so forth, but all of these require the above-mentioned Ti-based barrier metal, leading to the problem of worsening dark current.
The present invention was conceived in light of the above problems, and it is an object thereof to provide a solid-state imaging device having contact connection in an overflow drain or the like, with which increases in dark current can be suppressed while increases in contact resistance and the production of alloy spikes can be prevented, and also to provide a method for manufacturing a solid-state imaging device, with which the above-mentioned solid-state imaging device can be formed.
In order to achieve the stated object, the solid-state imaging device of the present invention comprises a semiconductor substrate of a first conduction type, a semiconductor layer of a second conduction type formed on the main surface of the semiconductor substrate, a separation region of a first conduction type formed on the main surface of the semiconductor substrate so as to demarcate the semiconductor layer, an annular first semiconductor region of a first conduction type formed adjacent to the separation region within the semiconductor layer demarcated by the separation region on the main surface of the semiconductor substrate, a second semiconductor region of a second conduction type formed touching the first semiconductor region on the inside of the first semiconductor region on the main surface of the semiconductor substrate, a first insulating film formed annularly over the first semiconductor region, and an electrode formed over the first insulating film so as to be contiguous with the second semiconductor region via an opening formed in the first insulating film, wherein the electrode is made up of aluminum containing copper, and a charge sweeping component is constituted by the first semiconductor region, the second semiconductor region, the first insulating film, and the electrode.
Preferably, the copper is contained in the solid-state imaging device of the present invention in an amount of 0.4 to 5 wt %, and even more preferably 0.5 to 0.8 wt %.
The solid-state imaging device of the present invention makes use of copper-containing aluminum as the material of the electrode directly connected to the silicon layer or other conductive layer and the contacts and so forth in a lateral overflow drain (LOD). By using aluminum containing copper for the material of the electrode, increases in dark current in the solid-state in dark current in the solid-state imaging device can be suppressed while increases in contact resistance and the production of alloy spikes can be prevented.
If the copper is contained in the aluminum in an amount less than 0.4 wt %, it will not be sufficient to prevent the production of alloy spikes, so greater restrictions will be imposed on the manufacturing process temperature in order to prevent these alloy spikes, making manufacture more difficult. On the other hand, if the copper content is over 5 wt %, the material will not lend itself to etching and other types of working, again making manufacture more difficult. The best range for the above-mentioned copper content is 0.5 to 0.8 wt %, within which the effects of the present invention can be easily realized without sacrificing workability and so on.
Also, in order to achieve the stated object, the method of the present invention for manufacturing a solid-state imaging device comprises the steps of forming a semiconductor layer of a second conduction type on the main surface of a semiconductor substrate of a first conduction type, forming a separation region of a first conduction type for demarcating the semiconductor layer on the main surface of the semiconductor substrate, forming a first insulating layer over the semiconductor layer, forming a first opening by etching the first insulating layer, through which the semiconductor layer demarcated by the separation region is exposed within the semiconductor layer, forming a first semiconductor region of a first conduction type by the implantation of impurities of a first conduction type using the first insulating layer as a mask, forming a second insulating layer over the first insulating layer including the first opening, etching the entire surface of the second insulating layer and thereby forming an annular first insulating film around the periphery of the first opening, and forming a second opening through which the semiconductor layer is exposed on the inside of the first insulating film, forming a second semiconductor region of a second conduction type on the inside of the first semiconductor region by the implantation of impurities of a second conduction type using the first insulating film as a mask, and forming over the first insulating film an electrode that is connected to the second semiconductor region via the second opening, wherein the electrode is made up of aluminum containing copper.
The above-mentioned electrode is preferably formed by coherent sputtering in the method of the present invention for manufacturing a solid-state imaging device.
Also, a sintering treatment is preferably carried out at a temperature of 350xc2x0 C. or lower after the step of forming the electrode in the method of the present invention for manufacturing a solid-state imaging device.
Also, the copper content is preferably 0.4 to 5 wt %, and even more preferably 0.5 to 0.8 wt %, in the method of the present invention for manufacturing a solid-state imaging device.
The method of the present invention for manufacturing a solid-state imaging device involves the use of copper-containing aluminum for the material of the electrode, which suppresses increases in dark current in the solid-state imaging device while preventing increases in contact resistance and the production of alloy spikes in the manufacture of the solid-state imaging device. Furthermore, the electrode composed of copper-containing aluminum is formed by coherent sputtering, which prevents contact coverage flaws from occurring. The sintering treatment carried out after the electrode formation is conducted at a temperature of 350xc2x0 C. or lower, effectively preventing the production of alloy spikes.
If the copper content in the aluminum is less than 0.4 wt %, it will not be sufficient to prevent the production of alloy spikes, so greater restrictions will be imposed on the manufacturing process temperature in order to prevent these alloy spikes, making manufacture more difficult. On the other hand, if the copper content is over 5 wt %, the material will not lend itself to etching and other types of working, again making manufacture more difficult. The best range for the above-mentioned copper content is 0.5 to 0.8 wt %, within which the effects of the present invention can be easily realized without sacrificing workability and so on.